Intel Network Card 8 LAN User Manual

Intel® I/O Controller Hub 8 LAN  
NVM Map and Information Guide  
January 2008  
316234-006  
Revision 2.8  
 
NVM Information Guide—ICH8  
Contents  
1.0 Non-Volatile Memory (NVM)......................................................................................5  
ICH8 NVM Contents and Sample Images.................................................................. 23  
Tables  
®
Device IDs for Intel Platform LAN Connects ............................................................... 12  
3
 
ICH8—NVM Information Guide  
Revision History  
Rev  
2.8  
Rev Date  
Description  
Updated bit descriptions for words 0Fh, 13h, 14h, 15h, 16h, 32h, and 33h.  
Updated NVM images in Appendix A.  
Jan 2008  
2.7  
2.6  
2.5  
Oct 2007  
April 2007  
April 2007  
Updated word 19h bit descriptions. Removed section 1.5.  
Updated Table 15 (bits 13:12 description) and Table 24 (word 0Fh).  
Removed all references to ICH9. Minor edit all sections.  
Updated sections 1.2, 1.4.6, 1.4.13, 1.4.14, 1.4.19, and 1.4.20.  
Added sections 1.4.25.1 through 1.4.25.4 (PXE words 30h through 33h).  
2.4  
Jan 2007  
2.3  
2.2  
2.1  
Jan 2007  
Oct 2006  
July 2006  
Added ICH9 and 82567 NVM information.  
Added device IDs for the 82562G and 82562GT 10/100 Mb/s Platform LAN Connects.  
Changed bit 1 of word 13h to 0b.  
Initial public release.  
Added new LAN Word Offset 19h description to Tables 1 and 17.  
Added new EEPROM images to Appendix A.  
Updated bit defaults and descriptions to Tables 9, 10, 13, 15, and 16.  
2.0  
June 2006  
April 2006  
1.75  
Updated bit descriptions for words 13h, 14h, and 19h.  
Initial Intel Confidential release.  
Converted this to a stand-alone document. Previously, it was AP-478 Addendum.  
Added Section 1.1, ”NVM Programming Procedure Overview,and Section 1.2,  
”EEUPDATE Utility.”  
Updated the following sections:  
Section 2.12, ”Shared Initialization Control (Word 13h),bits 10 and 0  
Section 2.13, ”Extended Configuration Word 1 (Word 14h),bits 15, 14, and 11:0  
Section 2.14, ”Extended Configuration Word 2 (Word 15h),bits 15:8  
Section 2.15, ”Extended Configuration Word 3 (Word 16h)”  
Section 2.16, ”LED 1 Configuration and Power Management (Word 17h),bit 7  
Section 2.17, ”LED 0 and 2 Configuration Defaults (Word 18h),bit 7  
Section 2.18, ”Future Initialization Word 1 (Words 19h)”  
Section 2.20, ”Checksum (Word 3Fh)”  
1.5  
Feb 2006  
Appendix A.1 ”82566DM NVM Image with ICH8”  
Appendix A.3 ”82562V NVM Image with ICH8”  
Updated Section 2.12, ”Shared Initialization Control (Word 13h),” Table 9 to add the  
Ext Pwr Polarity bit.  
Added the 82566 NVM image to A.1 ”82566DM NVM Image with ICH8.”  
1.0  
Dec 2005  
July 2005  
0.75  
Initial release (Intel Secret).  
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ICH8—NVM Information Guide  
1.0  
Non-Volatile Memory (NVM)  
1.1  
Introduction  
The document is intended for designs using the 10/100/1000 Mb/s LAN controller that  
®
is integrated into the Intel I/O Control Hub 8 (ICH8) device.  
The NVM space is used for hardware and software configuration. It is also read by  
software to determine and configure specific design features.  
Unless otherwise specified, all numbers in this document use the following numbering  
convention:  
• Numbers that do not have a suffix are decimal (base 10).  
• Numbers with a suffix of “h” are hexadecimal (base 16).  
• Numbers with a suffix of “b” are binary (base 2).  
1.2  
NVM Programming Procedure Overview  
The LAN NVM shares space on an SPI Flash device (or devices) along with the BIOS,  
Manageability Firmware, and a Flash Descriptor Region. It is programmed through the  
ICH8. This combined image is shown in Figure 1. The Flash Descriptor Region is used to  
define vendor specific information and the location, allocated space, and read and write  
permissions for each region. The Manageability (ME) Region contains the code and  
®
configuration data for ME functions such as Intel Active Management Technology, ASF,  
and Advanced Fan Speed Control. The system BIOS is contained in the BIOS Region.  
The ME Region and BIOS Region are beyond the scope of this document and a more  
®
detailed explanation of these areas can be found in the Intel I/O Controller Hub 8  
(ICH8) Family External Design Specification (ICH8 EDS). This document describes the  
LAN image contained in the Gigabit Ethernet (GbE) region. Fast Ethernet (82562V)  
images are also described.  
5
 
     
NVM Information Guide—ICH8  
BIOS  
Region 1  
ME  
Region 2  
GbE  
Region 3  
Flash Descriptor  
Region 0  
Figure 1.  
LAN NVM Regions  
To access the NVM, it is essential to correctly setup the following:  
1. A valid Flash Descriptor Region must be present. Details for the Flash Descriptor  
Region are contained in the ICH8 EDS. The FTOOL.exeutility provides the easiest  
method of configuring this descriptor region. This process is described in detail in  
®
the Intel Active Management Technology OEM Bring-Up Guide.  
®
FTOOL.exeand the Intel Active Management Technology OEM Bring-Up Guide  
can be obtained as part of the Intel Active Client Manager kit on ARMS  
2. The GbE region must be part of the original image flashed onto the part.  
3. For Intel LAN tools and drivers to work correctly, the BIOS must set the VSCC  
register(s) correctly. This information is described in ICH8 EDS, section 24.1.  
4. The GbE region of the NVM must be accessible. To keep this region accessible, the  
Protected Range register of the GbE LAN Memory Mapped Configuration registers  
must be set to their default value of 0000 0000h. (The GbE Protected Range  
registers are described in the ICH8 EDS).  
5. If you are using the 82566, the ICH8 soft strap for the GLCI interface must be set  
correctly. Bit 19 of STRP0 must be set to 1b (as described in the ICH8 EDS). For the  
82562V, this bit can be set to 0b, since it does not use the GLCI bus.  
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ICH8—NVM Information Guide  
6. The sector size of the NVM must equal 256 bytes, 4 KB, or 64 KB. When a Flash  
device that uses a 64 KB sector erase is used, the GbE region size must equal  
128 KB. If the Flash part uses a 4 KB or 256-byte sector erase, then the GbE region  
size must be set to 8 KB.  
The NVM image contains both static and dynamic data. The static data is the basic  
platform configuration, and includes OEM specific configuration bits as well as the  
unique Printed Circuit Board Assembly (PBA). The dynamic data holds the product’s  
Ethernet Individual Address (IA) and Checksum. This file can be created in a simple  
text editor and follows the format shown in Appendix A, which provides examples of  
GbE Region NVM maps for ICH8-based designs. Fast Ethernet (82562V) images are  
also provided.  
1.3  
EEUPDATE Utility  
Intel has created an EEUPDATE utility that can be used to update the GbE region  
images during in-circuit programming. The tool uses two basic data files outlined in the  
following section (static data file and IA address file). The EEUPDATE utility is flexible  
and can be used to update the entire GbE region image or only the IA address of the  
LAN controller. In addition, it also corrects the GbE component checksum field after the  
region is modified (FTOOL does not have this ability). For more information on how to  
use EEUPDATE, refer to the eeupdate.txtfile that is included with the EEUPDATE  
utility.  
To obtain a copy of this program, contact your Intel representative.  
1.3.1  
Command Line Parameters  
The DOS command format is as follows:  
EEUPDATE Parameter_1 Parameter_2  
where:  
Parameter_1 = /D or /A  
/D is used to update the entire GbE region image.  
/A is used to update just the Ethernet Individual Address.  
Parameter_2 = filename  
In Example 1, Parameter_2 is file1.eep, which contains the complete NVM image in  
a specific format used to update the complete GbE region. All comments in the .eep  
file must be preceded by a semicolon (;).  
Example 1. EEUPDATE /D file1.eep  
In Example 1, Parameter 2 is file2.dat, which contains a list of IA addresses. The  
EEUPDATE utility finds the first unused address from this file and uses it to update the  
NVM. An address is marked used if it is followed by a date stamp. When the utility uses  
a specific address, a log file called eelog.dat is updated with that address. This updated  
file should be used as the .datfile for the next update.  
Appendix A provides an example of the raw GbE region contents. Fast Ethernet  
(82562V) images are also provided.  
7
 
   
NVM Information Guide—ICH8  
1.4  
LAN NVM Format and Contents  
Table 1 lists the NVM maps for the LAN region. Each word listed is described in detail in  
the following sections.  
Table 1.  
LAN NVM Address Map  
LAN  
Word  
Offset  
NVM  
Byte  
Offset  
Image  
Value  
HIgh Byte (Bits 15:8)  
Low Byte (Bits 7:0)  
Used By  
Ethernet Individual Address  
Byte 2  
Ethernet Individual Address  
Byte 1  
HW-  
Shared  
00h  
01h  
02h  
00  
02  
04  
IA (2,1)  
IA (4,3)  
IA (6,5)  
Ethernet Individual Address  
Byte 4  
Ethernet Individual Address  
Byte 3  
HW-  
Shared  
Ethernet Individual Address  
Byte 6  
Ethernet Individual Address  
Byte 5  
HW-  
Shared  
03h  
04h  
05h  
06h  
07h  
08h  
09h  
0Ah  
0Bh  
0Ch  
0Dh  
0Eh  
0Fh  
10h  
11h  
12h  
06  
Reserved  
SW  
SW  
0800h  
FFFFh  
08  
Reserved  
Image Version Information 1  
Reserved  
0A  
SW  
0Ch  
0Eh  
10h  
12h  
14h  
16h  
18h  
1Ah  
1Ch  
1Eh  
20h  
22h  
24h  
SW  
FFFFh  
FFFFh  
Reserved  
SW  
PBA Low  
SW  
PBA High  
SW  
PCI Initialization Control Word  
Subsystem ID  
Subsystem Vendor ID  
Device ID  
HW-PCI  
HW-PCI  
HW-PCI  
HW-PCI  
HW-PCI  
HW-PCI  
HW-PCI  
Vendor ID  
Device REV ID  
LAN Power Consumption  
Reserved  
Reserved  
HW-  
Shared  
13h  
14h  
15h  
16h  
17h  
18h  
19h  
1Ah  
26h  
28h  
2Ah  
2Ch  
2Eh  
30h  
32h  
34h  
Shared Initialization Control Word  
Extended Configuration Word 1  
Extended Configuration Word 2  
Extended Configuration Word 3  
LEDCTL 1  
HW-  
Shared  
HW-  
Shared  
HW-  
Shared  
HW-  
Shared  
HW-  
Shared  
LEDCTL 0 2  
HW-  
Shared  
Future Initialization Word 1  
Future Initialization Word 2  
0000h  
0000h  
HW-  
Shared  
8
 
   
ICH8—NVM Information Guide  
LAN  
Word  
Offset  
NVM  
Byte  
Offset  
Image  
Value  
HIgh Byte (Bits 15:8)  
Low Byte (Bits 7:0)  
Used By  
1Bh to  
2Fh  
32h to  
5Eh  
Reserved  
30h to  
3Eh  
60h to  
7Ch  
PXE Software Region  
PXE  
SW  
3Fh  
7Eh  
Software Checksum (bytes 00h through 7Dh)  
Notes:  
1.  
2.  
3.  
4.  
SW = Software: This is access from the network configuration tools and drivers.  
PXE = PXE Boot Agent: This is access from the PXE Option ROM code in BIOS.  
HW-Shared = Hardware - Shared: This is read on when the Shared Configuration is reset.  
HW-PCI = Hardware - PCI: This is read when the PCI Configuration is reset.  
1.4.1  
Ethernet Individual Address (Words 00h - 02h)  
The Ethernet Individual Address (IA) is a six-byte field that must be unique for each  
adapter card or LOM and unique for each copy of the NVM image. The first three bytes  
are vendor specific. (For example, these bytes equal 00 AA 00 or 00 A0 C9 for Intel  
products.) The last three bytes must be unique for each copy of the NVM. OEM versions  
of the product might be required to have non-Intel ID’s in the first three byte positions.  
The value from this field is loaded into the Receive Address Register 0 (RAL0/RAH0).  
The Intel default is listed in Table 2.  
Table 2.  
Ethernet Individual Address (Words 00h - 02h)  
Individual Address Byte  
Word 00  
Word 01  
Word 02  
Byte  
2
Byte  
1
Byte  
4
Byte  
3
Byte  
6
Byte  
5
Manufacturer  
MAC Address  
Intel (original)  
Intel (new)  
00AA00XXYYZZh  
00A0C9XXYYZZh  
AAh  
A0h  
00h  
00h  
XXh  
XXh  
00h  
C9h  
ZZh  
ZZh  
YYh  
YYh  
Note:  
The Ethernet IA is byte swapped, as listed in Table 2.  
The IA bytes read from the NVM are used by the ICH8 until an IA Setup command is  
issued by software. The IA defined by the IA Setup command overrides the IA read  
from the NVM.  
1.4.2  
Reserved (Word 03h)  
Table 3.  
Reserved (Word 03h)  
Bit  
Name  
Default  
Description  
15:12 Reserved  
0000b  
1b  
These bits are reserved and should be set to 0000b.  
Must be set to 1b for Intel Boot Agent (IBA) to function correctly.  
These bits are reserved and should be set to 0h.  
11  
IBA LOM  
Reserved  
10:0  
0h  
9
 
       
NVM Information Guide—ICH8  
1.4.3  
Reserved (Word 04h)  
Table 4.  
Reserved (Word 04h)  
Bit  
Name  
Reserved  
Default  
Description  
These bits are reserved and should be set to FFFFh.  
15:0  
FFFFh  
1.4.4  
Image Version Information (Word 05h)  
Table 5.  
Image Version Information (Word 05h)  
Bit  
Name  
Default  
Description  
15  
Reserved  
0b  
--  
This bit is reserved and should be set to 0b.  
14:12 NVM Major Version  
This field represents the LAN NVM major version number.  
This field represents the LAN NVM minor version number.  
11:4  
3:0  
NVM Minor Version  
Image ID  
--  
This field represents the NVM image identification. This field equals  
2h (default) for the 82562V PHY and 0h for the 82566 PHY.  
2h  
1.4.5  
Reserved (Word 06h)  
Table 6.  
Reserved (Word 06h)  
Bit  
Name  
Reserved  
Default  
Description  
15:0  
FFFFh  
This field is reserved and should be set to FFFFh.  
1.4.6  
Reserved (Word 07h)  
Table 7.  
Reserved (Word 07h)  
Bit  
Name  
Reserved  
Default  
Description  
15:0  
FFFFh  
This field is reserved and should be set to FFFFh.  
1.4.7  
PBA Low, PBA High (Words 08h and 09h)  
The nine digit printed board assembly (PBA) number used for Intel manufactured  
adapter cards are stored in a four-byte field. The dash and the first digit of the three-  
digit suffix are not stored.  
1.4.7.1  
PBA Example  
If the PBA Number is “123456-003”  
then word 08h = 1234h and word 09h = 5603h.  
Through the course of hardware changes, the suffix field (byte 4) is incremented. The  
purpose of this information is to enable customer support (or any user) to identify the  
exact revision level of a product. The software device driver should not rely on this field  
to identify the product or its capabilities.  
10  
 
                 
ICH8—NVM Information Guide  
1.4.8  
PCI Initialization Control (Word 0Ah)  
This word contains initialization values that:  
• Set defaults for some internal registers.  
• Enable/disable specific features.  
• Determine which PCI configuration space values are loaded from the NVM.  
Table 8.  
PCI Initialization Control Word (Word 0Ah)  
Bit  
Name  
Default  
Description  
15:13 Reserved  
000b  
1b  
This field is reserved and should be set to 000b.  
This field is reserved and should be set to 1b.  
These bits are reserved and should be set to 0000b.  
12  
Reserved  
Reserved  
11:8  
0000b  
This bit is used as an auxiliary power indication. It is used in  
conjunction with the PM Enable bit.  
7
AUX PWR  
1b  
0b = D3cold wake-up is not advertised.  
1b = D3cold wake-up is advertised in the PMC register of the PCI  
function if the PM Enable bit is also set.  
This bit enables the assertion of a PME in the PCI function at any  
power state.  
0b = PME functionality is disabled.  
1b = PME functionality is enabled.  
6
PM-Ena  
1b  
This bit affects the advertised PME_Support indication in the PMC  
register of the PCI function.  
5:3  
2
Reserved  
APM Enable  
00b  
1b  
This bit is reserved and should be set to 00b.  
When APM Enable is set, both the PHY (82566 or 82562V) and  
the MAC should be initialized to a functional state following power  
up.  
0b = APM functionality is disabled.  
1b = APM functionality is enabled.  
Note: This is a reserved bit for the ICH8 (B1 stepping).  
0b = Device loads the default PCI Subsystem ID and Subsystem  
Vendor ID.  
1b = Device loads its PCIe* Subsystem ID and Subsystem Vendor  
ID from the NVM (words 0Bh and 0Ch).  
1
0
Load Subsystem IDs 1b  
0b = Device loads the default PCI Vendor and Device IDs.  
1b = Device loads the default values for PCI Vendor and Device IDs  
from the NVM (words 0Dh and 0Eh).  
Load Vendor/Device  
1b  
IDs  
1.4.9  
Subsystem ID (Word 0Bh)  
If Load Subsystem IDs bit of word 0Ah is set to 1b, this word is read in to initialize the  
Subsystem ID. The Subsystem ID default value is 0000h.  
1.4.10  
Subsystem Vendor ID (Word 0Ch)  
If Load Subsystem IDs bit of word 0Ah is set to 1b, this word is read in to initialize the  
Subsystem Vendor ID. The Subsystem Vendor ID default value is 8086h.  
11  
 
       
NVM Information Guide—ICH8  
1.4.11  
Device ID (Word 0Dh)  
If the Load Vendor/Device IDs bit in word 0Ah is set to 1b, this word is read to initialize  
the Device ID of the LAN function.  
®
Table 9.  
Device IDs for Intel Platform LAN Connects  
Device ID  
Adapter  
1049h  
104Ah  
104Dh  
104Ch  
Intel® 82566MM Gigabit Ethernet Controller  
Intel® 82566DM Gigabit Ethernet Controller  
Intel® 82566MC Gigabit Ethernet Controller  
Intel® 82562V 10/100 Mb/s Platform LAN Connect Device  
1.4.12  
1.4.13  
Vendor ID (Word 0Eh)  
If the Load Vendor/Device IDs bit in word 0Ah is set to 1b, this word is read to initialize  
the Vendor ID. The default Vendor ID value is 8086h.  
Device Rev ID (word 0Fh)  
Bit  
Name  
Default  
Description  
15:0  
Reserved  
00h  
Reserved  
1.4.14  
LAN Power Consumption (Word 10h)  
This word is only relevant when power management is enabled.  
Table 10.  
LAN Power Consumption (Word 10h)  
Bit  
Name  
Default  
Description  
The value in this field is reflected in the PCI Power Management  
Data Register of the LAN function for D0 power consumption and  
dissipation (Data_Select = 0 or 4). Power is defined in 100 mW  
units and includes the external logic required for the LAN function.  
0Dh for 82566  
LAN D0  
Power  
15:8  
7:5  
04h for 82562V  
Reserved 000b  
These bits are reserved and should be set to 000b.  
The value in this field is reflected in the PCI Power Management  
Data Register of the LAN function for D3 power consumption and  
dissipation (Data_Select = 3 or 7). Power is defined in 100 mW  
units and includes the external logic required for the LAN function.  
The most significant bits in the Data Register that reflects the  
power values are padded with zeros.  
00001b for 82566  
00010b for 82562V  
LAN D3  
Power  
4:0  
12  
 
           
ICH8—NVM Information Guide  
1.4.15  
Shared Initialization Control (Word 13h)  
This word controls general initialization values.  
Table 11.  
Shared Initialization Control (Word 13h)  
Bit  
Name  
Default  
Description  
Valid Indication  
This is a 2-bit field indicating whether a valid NVM is present to the  
MAC. If this field does not equal 10b, the MAC does not read the  
NVM data and uses default values for device configuration.  
00b = Invalid NVM.  
01b = Invalid NVM.  
10b = Valid NVM present.  
11b = Invalid NVM.  
15:14 SIGN  
10b  
13:11 Reserved  
010b  
1b  
These bits are reserved and should be set to 010b.  
Reserved. Always set to 1b.  
10  
Reserved  
For ICH8 designs that support an ACBS implementation using LAN  
Power Control (LAN_PHYPC), this bit enables or disables PHY power  
down.  
0b = PHY power down feature is disabled.  
1b = PHY power down feature is enabled to power down at DMoff/  
D3 without Wake on LAN.  
9
PHY PD Ena  
1b  
This bit is loaded to the PHY Power Down Enable bit in the  
CTRL_EXT register.  
8
Reserved  
PHYT  
0b  
This bit is reserved and should be set to 0b.  
This field indicates the PHY device type.  
00b = 82566 PHY - GLCI mode  
01b = Reserved  
10b = 82562V PHY - PCIe mode, LCI mode  
11b = Reserved  
7:6  
00b  
This field is reflected in the PHYTYPE field in the Status register.  
5
4
Reserved  
FRCSPD  
0b  
0b  
Reserved. Must be set to 0b.  
Force Speed Enable  
0b = Normal operation.  
1b = Use ICH8 speed.  
Force Duplex  
3
2
FD  
0b  
1b  
0b = Normal operation.  
1b = Use ICH8 speed.  
This bit is loaded to the CTRL_EXT.EnaKumCK16 bit and enables  
the reduction of the internal JCLK to one-sixteenth of the external  
NJCLK at the GLCI interface in Gigabit Ethernet mode.  
0b = Reduction is disabled.  
1b = Reduction is enabled.  
CLK_CNT_1_16  
This bit enables the automatic reduction of DMA frequency. It is  
mapped to STATUS[31].  
0b = Automatic reduction disabled.  
1b = Automatic reduction enabled.  
1
0
CLK_CNT_1_4  
0b  
1b  
Dynamic Clock Gating  
0b = Disable.  
1b = Enable.  
Dynamic Clock  
Gating  
13  
 
   
NVM Information Guide—ICH8  
1.4.16  
Extended Configuration Word 1 (Word 14h)  
Table 12.  
Extended Configuration Word 1 (Word 14h)  
Bit  
15  
Name  
Reserved  
Default  
Description  
Reserved. Must be set to 0b.  
0b  
1b = ICH8 (B0/B1 stepping).  
0b = ICH8 (A0 stepping).  
14  
13  
Reserved  
Reserved  
1b  
1b  
Set this field to 0b.  
OEM Write Enable  
0b = Disable.  
1b = Enable.  
12  
OEM Write Enable  
1b  
Set this field to 0b.  
Extended  
Configuration  
Pointer  
This field defines the base address (in Dwords) of the extended  
configuration area in the NVM. It should equal a non-zero value.  
11:0  
020h  
1.4.17  
Extended Configuration Word 2 (Word 15h)  
Table 13.  
Extended Configuration Word 2 (Word 15h)  
Bit  
Name  
Default  
Description  
This field identifies the size (in Dwords) of the extended PHY  
configuration area.  
For the 82566 PHY, if the extended PHY configuration area is  
Extended PHY  
Length  
15:8  
7:0  
37h  
00h  
disabled, the length must be set to 37h.  
Reserved  
These bits are reserved and should be set to 00h.  
1.4.18  
Extended Configuration Word 3 (Word 16h)  
Table 14.  
Extended Configuration Word 3 (Word 16h)  
Bit  
Name  
Reserved  
Default  
Description  
15:0  
00h  
These bits are reserved and should be set to 00h.  
14  
 
           
ICH8—NVM Information Guide  
1.4.19  
LED 1 Configuration and Power Management (Word 17h)  
This field specifies the default values for the LEDCTL register fields controlling the LED1  
(LINK_1000) output behaviors and the OEM fields defining the PHY power management  
parameters loaded to the PHY_CTRL register.  
Table 15.  
LED 1 Configuration and Power Management (Word 17h)  
Bit  
Name  
Default  
Description  
This bit enables Smart Power Down in back-to-back link setup.  
0b = B2B disabled.  
15  
B2B Enable  
1b  
1b = B2B enabled.  
GbE Disable (in all power states)  
0b = GbE enabled.  
14  
GbE Disable  
0b  
1b = GbE disabled.  
13:12 Reserved  
00b  
1b  
These bits are reserved and should be set to 00b.  
GbE Disable (in all power states except D0a)  
0b = GbE enabled.  
1b = GbE disabled.  
GbE Disable in non-  
11  
D0a  
The Low Power Link Up enables link at the lowest speed supported  
by both link partners in non-D0a states. This bit must be set if  
LPLU Enable bit is set.  
0b = Low Power Link Up is disabled.  
1b = Low Power Link Up is enabled in all non-D0a states.  
LPLU Enable in non-  
D0a  
10  
1b  
0b  
The Low Power Link Up enables link at the lowest speed supported  
by both link partners in all power states. This bit enables a  
decrease in link speed in all power states.  
9
LPLU Enable  
0b = Low Power Link Up is disabled.  
1b = Low Power Link Up is enabled in all power states.  
0b = PHY Smart Power Down mode is disabled.  
1b = PHY Smart Power Down mode is enabled.  
8
7
SPD Enable  
LED1 Blink  
1b  
0b  
This bit indicates the initial value of the LED1_BLINK field.  
0b = LED1 is non-blinking (recommended).  
1b = LED1 is blinking.  
This bit indicates the initial value of the LED1_IVRT field.  
0b = LED1 has an active low output.  
1b = LED1 has an active high output.  
6
5
LED1 Invert  
0b  
0b  
This bit defines the LED1 blink mode:  
0b = Blink at 200 ms on and 200 ms off.  
1b = Blink at 83 ms on and 83 ms off.  
This field should be identical to LED0 Blink Mode.  
LED1 Blink Mode  
Enable Filtered Activity LED (while operating with the 82562V)  
When set to 0b, the activity LED is activated by the PHY.  
4
Filtered ACT LED  
LED1 Mode  
0b  
When set to 1b, the activity LED is driven by Tx activity or Rx  
traffic that match any of the MAC's MAC addresses.  
For the 82566, this bit is reserved and should be set to 0b.  
These bits represent the initial value of the LED1_MODE field,  
which specifies the event, state, or pattern displayed on LED1  
(LINK_1000) output. Table 16 defines the values for LED1 Mode.  
3:0  
0111b  
A value of 0111b indicates that a 1000 Mb/s link is established and  
maintained.  
The following table lists the LED modes defined in bits 3:0 of this word.  
15  
 
   
NVM Information Guide—ICH8  
Table 16.  
LED Modes  
Mode (Bits  
3:0)  
Selected Mode  
Source Indication  
Asserted when either 10 Mb/s or 1000 Mb/s link is established  
and maintained.  
0000b  
LINK_10/1000  
Asserted when either 100 Mb/s or 1000 Mb/s link is  
established and maintained.  
0001b  
0010b  
0011b  
LINK_100/1000  
LINK-UP  
Asserted when any speed link is established and maintained.  
Asserted when link is established and packets are being  
transmitted or received that passed MAC filtering.  
FILTER_ACTIVITY  
Asserted when link is established and when there is no  
transmit or receive activity.  
0100b  
LINK/ACTIVITY  
0101b  
0110b  
0111b  
1000b  
1001b  
1010b  
LINK_10  
LINK_100  
Asserted when a 10 Mb/s link is established and maintained.  
Asserted when a 100 Mb/s link is established and maintained.  
Asserted when a 1000 Mb/s link is established and maintained.  
Reserved.  
LINK_1000  
Reserved  
FULL_DUPLEX  
COLLISION  
Asserted when the link is configured for full duplex operation.  
Asserted when a collision is observed.  
Asserted when link is established and packets are being  
transmitted or received.  
1011b  
ACTIVITY  
1100b  
1101b  
1110b  
1111b  
BUS_SIZE  
PAUSED  
LED_ON  
LED_OFF  
Asserted when the MAC detects a 1-lane PCIe* connection.  
Asserted when the MAC transmitter is flow controlled.  
Always asserted.  
Always de-asserted.  
1.4.20  
LED 0 and 2 Configuration Defaults (Word 18h)  
This NVM word specifies the hardware defaults for the LEDCTL register fields controlling  
the LED0 (LINK/ACTIVITY) and LED2 (LINK_100) output behaviors.  
Table 17.  
LED 0 and 2 Configuration Defaults (Word 18h)  
Bit  
Name  
Default  
Description  
This bit indicates the initial value of the LED2_BLINK field.  
0b = LED2 is non-blinking.  
15  
LED2 Blink  
0b  
1b = LED2 is blinking.  
This bit indicates the initial value of the LED2_IVRT field.  
0b = LED2 has an active low output.  
1b = LED2 has an active high output.  
14  
13  
LED2 Invert  
0b  
0b  
This bit defines the LED2 blink mode:  
0b = Blink at 200 ms on and 200 ms off.  
1b = Blink at 83 ms on and 83 ms off.  
LED2 Blink Mode  
Note: This field should be identical to the LED0 Blink Mode.  
12  
Reserved  
0b  
This bit is reserved and should be set to 0b.  
These bits represent the initial value of the LED2_MODE field,  
which specifies the event, state, or pattern displayed on LED2  
(LINK_100) output. A value of 0110b causes this to indicate  
100 Mb/s operation.  
11:8  
LED2 Mode  
0110b  
16  
 
     
ICH8—NVM Information Guide  
Table 17.  
LED 0 and 2 Configuration Defaults (Word 18h)  
Bit  
Name  
Default  
Description  
This bit indicates the initial value of the LED0_BLINK field.  
0b = LED0 is non-blinking (recommended).  
1b = LED0 is blinking.  
7
6
LED0 Blink  
1b  
This bit indicates the initial value of the LED0_IVRT field.  
0b = LED0 has an active low output.  
1b = LED0 has an active high output.  
LED0 Invert  
0b  
0b  
This bit define the LED0 blink mode:  
0b = Blink at 200 ms on and 200 ms off.  
1b = Blink at 83 ms on and 83 ms off.  
Note: This field initializes the GLOBAL_BLINK_MODE field in the  
LEDCTL register.  
5
4
LED0 Blink Mode  
Reserved  
0b  
This bit is reserved and should be set to 0b.  
These bits represent the initial value of the LED0_MODE field,  
which specifies the event, state, or pattern displayed on LED0  
(Link/Activity) output. Table 16 defines the values for LED0 Mode.  
3:0  
LED0 Mode  
0100b  
Table 16, “LED Modes” above summarizes the LED modes defined in bits 3:0 of this  
word.  
1.4.21  
1.4.22  
Future Initialization Word 1 (Words 19h)  
Bit  
Name  
Default  
Description  
This field is loaded to bits 15:0 of the FEXTNVM register.  
For the 82562V, must be set to 301h.  
For 82566 SKUs that include ACBS, must be set to 181h.  
For 82566 SKUs without ACBS, must be set to 301h.  
15:0  
Reserved  
X
Future Init Word 2 (Word 1Ah)  
Bit  
Name  
Default  
Description  
Reserved  
This field is loaded to bits 15:0 of the FEXTNVM register.  
For ICH8, set these bits to 0800h.  
15:0  
Reserved  
X
For ICH8M:  
All 82566 SKUs that include ACBS, must be set to 0803h.  
All 82566 SKUs without ACBS, must be set to 2803h.  
17  
 
   
NVM Information Guide—ICH8  
1.4.23  
PXE Words (Words 30h - 3Eh)  
Words 30h through 3Eh (bytes 60h through 7Dh) have been reserved for configuration  
and version values to be used by PXE code.  
1.4.23.1  
Boot Agent Main Setup Options (Word 30h)  
The boot agent software configuration is controlled by the NVM with the main setup  
options stored in word 30h. These options are those that can be changed by using the  
Control-S setup menu or by using the IBA Intel Boot Agent utility. Note that these  
settings only apply to Boot Agent software.  
Table 18.  
Boot Agent Main Setup Options  
Bit  
Name  
Description  
PXE Presence.  
Setting this bit to 0b Indicates that the image in the Flash contains a  
PXE image.  
Setting this bit to 1b indicates that no PXE image is contained.  
The default for this bit is 0b for backwards compatibility with existing  
systems already in the field.  
15  
PPB  
If this bit is set to 0b, EEPROM word 32h (PXE Version) is valid. When  
EPB is set to 1b and this bit is set to 0b, indicates that both images are  
present in the Flash.  
EFI Presence.  
Setting this bit to 1b Indicates that the image in the Flash contains an  
EFI image.  
Setting this bit to 0b indicates that no EFI image is contained.  
The default for this bit is 0b for backwards compatibility with existing  
systems already in the field.  
14  
EPB  
If this bit is set to 1b, EEPROM word 33h (EFI Version) is valid. When  
PPB is set to 0b and this bit is set to 1b, indicates that both images  
(PXE and EFI) are present in the Flash.  
13  
12  
Reserved  
FDP  
Reserved for future use. This bit must be set to 0b.  
Force Full Duplex.  
Set this bit to 0b for half duplex and 1b for full duplex.  
Note that this bit is a don’t care unless bits 10 and 11 are set.  
Force Speed.  
These bits determine speed.  
01b = 10 Mb/s  
11:10  
FSP  
10b = 100 Mb/s  
11b = Not allowed.  
All zeros indicate auto-negotiate (the current bit state).  
Note that bit 12 is a don’t care unless these bits are set.  
Reserved  
Set this bit to 0b.  
9
8
Reserved  
DSM  
Display Setup Message.  
If this bit is set to 1b, the "Press Control-S" message appears after the  
title message.  
The default for this bit is 1b.  
18  
 
   
ICH8—NVM Information Guide  
Bit  
Name  
Description  
Prompt Time. These bits control how long the "Press Control-S" setup  
prompt message appears, if enabled by DIM.  
00b = 2 seconds (default)  
01b = 3 seconds  
10b = 5 seconds  
7:6  
5
PT  
11b = 0 seconds  
Note that the Ctrl-S message does not appear if 0 seconds prompt time  
is selected.  
Reserved  
DBS  
Reserved  
Default Boot Selection. These bits select which device is the default  
boot device. These bits are only used if the agent detects that the BIOS  
does not support boot order selection or if the MODE field of word 31h  
is set to MODE_LEGACY.  
00b = Network boot, then local boot  
01b = Local boot, then network boot  
10b = Network boot only  
4:3  
11b = Local boot only  
2
Reserved  
PS  
Reserved  
Protocol Select. These bits select the boot protocol.  
00b = PXE (default value)  
01b = RPL protocol  
1:0  
Other values are undefined.  
1.4.23.2  
Boot Agent Configuration Customization Options (Word 31h)  
Word 31h contains settings that can be programmed by an OEM or network  
administrator to customize the operation of the software. These settings cannot be  
changed from within the Control-S setup menu or the IBA Intel Boot Agent utility. The  
lower byte contains settings that would typically be configured by a network  
administrator using the Intel Boot Agent utility; these settings generally control which  
setup menu options are changeable. The upper byte are generally settings that would  
be used by an OEM to control the operation of the agent in a LOM environment,  
although there is nothing in the agent to prevent their use on a NIC implementation.  
19  
 
NVM Information Guide—ICH8  
Table 19.  
Boot Agent Configuration Customization Options (Word 31h)  
Bit  
Name  
Description  
Signature. These bits must be set to 01b to indicate that this word has  
been programmed by the agent or other configuration software.  
15:14  
13:11  
SIG  
Reserved  
Reserved for future use. All bits must be set to 0b.  
Selects the agent's boot order setup mode. This field changes the  
agent's default behavior in order to make it compatible with systems  
that do not completely support the BBS and PnP Expansion ROM  
standards. Valid values and their meanings are:  
000b = Normal behavior. The agent attempts to detect BBS and PnP  
Expansion ROM support as it normally does.  
001b = Force Legacy mode. The agent does not attempt to detect BBS  
or PnP Expansion ROM supports in the BIOS and assumes the BIOS is  
not compliant. The BIOS boot order can be changed in the Setup Menu.  
010b = Force BBS mode. The agent assumes the BIOS is BBS-  
compliant, even though it may not be detected as such by the agent's  
detection code. The BIOS boot order CANNOT be changed in the Setup  
Menu.  
011b = Force PnP Int18 mode. The agent assumes the BIOS allows  
boot order setup for PnP Expansion ROMs and hooks interrupt 18h (to  
inform the BIOS that the agent is a bootable device) in addition to  
registering as a BBS IPL device. The BIOS boot order CANNOT be  
changed in the Setup Menu.  
10:8  
MODE  
100b = Force PnP Int19 mode. The agent assumes the BIOS allows  
boot order setup for PnP Expansion ROMs and hooks interrupt 19h (to  
inform the BIOS that the agent is a bootable device) in addition to  
registering as a BBS IPL device. The BIOS boot order CANNOT be  
changed in the Setup Menu.  
101b = Reserved for future use. If specified, treated as value 000b.  
110b = Reserved for future use. If specified, treated as value 000b.  
111b = Reserved for future use. If specified, treated as value 000b.  
7:6  
5
Reserved  
DFU  
Reserved for future use. These bits must be set to 0b.  
Disable Flash Update.  
If set to 1b, no updates to the Flash image using PROSet is allowed.  
The default for this bit is 0b; allow Flash image updates using PROSet.  
Disable Legacy Wakeup Support.  
If set to 1b, no changes to the Legacy OS Wakeup Support menu  
option is allowed.  
The default for this bit is 0b; allow Legacy OS Wakeup Support menu  
option changes.  
4
3
DLWS  
DBS  
Disable Boot Selection.  
If set to 1b, no changes to the boot order menu option is allowed.  
The default for this bit is 0b; allow boot order menu option changes.  
20  
 
 
ICH8—NVM Information Guide  
Bit  
Name  
Description  
Disable Protocol Select.  
2
1
DPS  
DTM  
If set to 1b, no changes to the boot protocol is allowed.  
The default for this bit is 0b; allow changes to the boot protocol.  
Disable Title Message.  
If set to 1b, the title message displaying the version of the boot agent  
is suppressed; the Control-S message is also suppressed. This is for  
OEMs who do not want the boot agent to display any messages at  
system boot.  
The default for this bit is 0b; allow the title message that displays the  
version of the boot agent and the Control-S message.  
Disable Setup Menu.  
If set to 1b, no invoking the setup menu by pressing Control-S is  
allowed. In this case, the EEPROM can only be changed via an external  
program.  
0
DSM  
The default for this bit is 0b; allow invoking the setup menu by  
pressing Control-S.  
1.4.23.3  
Table 20.  
Boot Agent Configuration Customization Options (Word 32h)  
Word 32h is used to store the version of the boot agent that is stored in the Flash  
image. When the Boot Agent loads, it can check this value to determine if any first-time  
configuration needs to be performed. The agent then updates this word with its  
version. Some diagnostic tools to report the version of the Boot Agent in the Flash also  
read this word. This word is only valid if the PPB is set to 0b. Otherwise the contents  
might be undefined.  
Boot Agent Configuration Customization Options (Word 32h)  
Bit  
Name  
Description  
15:12  
11:8  
7:0  
MAJOR  
MINOR  
BUILD  
PXE boot agent major version. The default for these bits is 0001b.  
PXE boot agent minor version. The default for these bits is 0010b.  
PXE boot agent build number. The default for these bits is 00101000b  
21  
 
 
NVM Information Guide—ICH8  
1.4.23.4  
Table 21.  
IBA Capabilities (Word 33h)  
Word 33h is used to enumerate the boot technologies that have been programmed into  
the Flash. It is updated by IBA configuration tools and is not updated or read by IBA.  
IBA Capabilities  
Bit  
Name  
Description  
Signature. These bits must be set to 01b to indicate that this word has  
been programmed by the agent or other configuration software.  
15:14  
13:5  
SIG  
Reserved  
Reserved for future use. All bits must be set to 0b.  
SAN capability is present in Flash.  
4
SAN  
0b = The SAN capability is not present (default).  
1b = The SAN capability is present.  
EFI UNDI capability is present in Flash.  
0b = The RPL code is not present (default).  
1b = The RPL code is present.  
3
2
1
EFI  
Reserved  
UNDI  
Reserved. Must be set to 0b.  
PXE/UNDI capability is present in Flash.  
1b = The PXE base code is present (default).  
0b = The PXE base code is not present.  
PXE base code is present in Flash.  
0
BC  
0b = The PXE base code is present.  
1b = The PXE base code is not present (default).  
1.4.24  
Checksum (Word 3Fh)  
The Checksum word (NVM bytes 7Eh and 7Fh) is used to ensure that the base NVM  
image is valid. Its value should be calculated by adding all words (00h through 3Fh)/  
bytes (00h-7Eh), including the Checksum word itself. The sum, including the  
Checksum, should equal BABAh. The initial value before the values are added together  
should be 0000h, and the carry bit should be ignored after each addition. If the OEM  
does not desire to calculate the checksum, LAD programming tools and drivers will  
detect if the checksum is incorrect and fix it in the image.  
Note:  
The default image always has a checksum value of 0. The default image always has a  
checksum value of 0b. The LAD programming tools (EEUPDATE or LANCONF) update  
the checksum when the image is programmed.  
22  
 
   
ICH8—NVM Information Guide  
Appendix A ICH8 NVM Contents and Sample Images  
This section contains a sample of raw NVM contents for the ICH8. All values for these  
images are hexadecimal.  
Table 22.  
LAN NVM Contents  
Word  
Description  
00:02h  
03:04h  
05h  
Ethernet Individual Address  
Reserved  
Image Version Information 1  
Reserved  
06:07h  
08:09h  
0Ah  
PBA Bytes  
PCI Initialization Control Word  
Subsystem ID  
0Bh  
0Ch  
Subsystem Vendor ID  
Device ID  
0Dh  
0Eh  
Vendor ID  
0Fh  
Device REV ID  
10h  
LAN Power Consumption  
Reserved  
11:12h  
13h  
Shared Initialization Control Word  
Extended Configuration Words  
LEDCTRL Words  
14:16h  
17:18h  
19h  
Future Initialization Word 1  
Future Initialization Word 2  
Reserved  
1Ah  
1B:2Fh  
30:3Eh  
3Fh  
PXE Software Region  
Software Checksum  
23  
 
   
NVM Information Guide—ICH8  
A.1  
82566DM NVM Image with ICH8  
0/8 1/9 2/A 3/B 4/C 5/D 6/E 7/F  
8888 8888 8887 0800 FFFF 1030 FFFF FFFF  
FFFF FFFF 10C7 0000 8086 104A 8086 0000  
0D01 0000 0000 9605 5020 3700 0000 8D07  
0684 0301 0000 0000 0000 0000 0000 0000  
0000 0000 0000 0000 0000 0000 0000 0000  
0000 0000 0000 0000 0000 0000 0000 0000  
0100 4000 1228 4007 FFFF FFFF FFFF FFFF  
FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF  
;
;-----------Range [0x40-0x7F]----------  
6100 001F 0404 0010 6120 001F 0E02 0012  
2F40 001F 901B 001B 0000 0012 2FA0 001F  
F8F0 0012 2000 001F 10B0 0010 0000 0011  
20C0 001F 249A 001D 00D3 001E 28A0 001F  
04CE 0014 2F60 001F 29E4 0010 0000 001F  
0140 0000 1F20 001F 1606 0010 B814 0011  
012A 0015 0067 001E 1F40 001F 0065 0014  
002A 0015 1F60 001F 3FB0 0012 C0FF 0016  
;
;-----------Range [0x80-0xBF]----------  
1DEC 0017 F9EF 0018 0210 0019 1880 001F  
0003 0015 D918 0018 1780 001F 0008 0016  
D008 0018 1860 001F 0800 001A 0000 001F  
1340 0000 0001 0019 2F40 001F 9018 001B  
0000 001F 1340 0000 6051 001F 0001 0011  
6100 001F 0400 0010 0000 001F FFFF FFFF  
FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF  
FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF  
;
24  
 
 
ICH8—NVM Information Guide  
A.2  
82566MM NVM Image with ICH8M  
Note:  
For use with ICH8 B-1 stepping only. Image has Intel® ACBS enabled.  
0/8 1/9 2/A 3/B 4/C 5/D 6/E 7/F  
8888 8888 8887 0800 FFFF 2000 FFFF FFFF  
FFFF FFFF 10C7 0000 8086 1049 8086 0000  
0D01 0000 0000 9605 5020 3700 0000 0D07  
0684 0181 0000 0000 0000 0000 0000 0000  
0000 0000 0000 0000 0000 0000 0000 0000  
0000 0000 0000 0000 0000 0000 0000 0000  
0100 4000 1228 4007 FFFF FFFF FFFF FFFF  
FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF  
;
;-----------Range [0x40-0x7F]----------  
6100 001F 0404 0010 6120 001F 0E02 0012  
2F40 001F 9018 001B 0000 0012 2FA0 001F  
8B24 0011 F8F0 0012 2000 001F 01B0 0010  
0000 0011 20C0 001F 249A 001D 00D3 001E  
28A0 001F 04CE 0014 2F60 001F 29E4 0010  
0000 001F 0140 0000 1F20 001F 1606 0010  
B814 0011 012A 0015 0067 001E 1F40 001F  
0065 0014 002A 0015 002A 0016 1F60 001F  
;
;-----------Range [0x80-0xBF]----------  
3FB0 0012 C0FF 0016 1DEC 0017 F9EF 0018  
0210 0019 1880 001F 0003 0015 1780 001F  
0008 0016 1780 001F D008 0018 1880 001F  
D918 0018 1860 001F 0800 001A 0000 001F  
0001 0019 1340 0000 6051 001F 0001 0011  
6100 001F 0400 0010 0000 001F FFFF FFFF  
FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF  
FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF  
;
25  
 
 
NVM Information Guide—ICH8  
A.3  
82566MC NVM Image with ICH8  
0/8 1/9 2/A 3/B 4/C 5/D 6/E 7/F  
8888 8888 8887 0800 FFFF 2000 FFFF FFFF  
FFFF FFFF 10C7 0000 8086 104D 8086 0000  
0D01 0000 0000 9605 5020 3700 0000 0D07  
0684 0181 0000 0000 0000 0000 0000 0000  
0000 0000 0000 0000 0000 0000 0000 0000  
0000 0000 0000 0000 0000 0000 0000 0000  
0100 4000 1228 4007 FFFF FFFF FFFF FFFF  
FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF  
;
;-----------Range [0x40-0x7F]----------  
6100 001F 0404 0010 6120 001F 0E02 0012  
2F40 001F 9018 001B 0000 0012 2FA0 001F  
8B24 0011 F8F0 0012 2000 001F 01B0 0010  
0000 0011 20C0 001F 249A 001D 00D3 001E  
28A0 001F 04CE 0014 2F60 001F 29E4 0010  
0000 001F 0140 0000 1F20 001F 1606 0010  
B814 0011 012A 0015 0067 001E 1F40 001F  
0065 0014 002A 0015 002A 0016 1F60 001F  
;
;-----------Range [0x80-0xBF]----------  
3FB0 0012 C0FF 0016 1DEC 0017 F9EF 0018  
0210 0019 1880 001F 0003 0015 1780 001F  
0008 0016 1780 001F D008 0018 1880 001F  
D918 0018 1860 001F 0800 001A 0000 001F  
0001 0019 1340 0000 6051 001F 0001 0011  
6100 001F 0400 0010 0000 001F FFFF FFFF  
FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF  
FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF  
;
26  
 
 
ICH8—NVM Information Guide  
A.4  
82562V NVM Image with ICH8  
0/8 1/9 2/A 3/B 4/C 5/D 6/E 7/F  
8888 8888 8887 0800 FFFF 1002 FFFF FFFF  
FFFF FFFF 10C7 0000 8086 104C 8086 0000  
0402 0000 0000 9687 4020 0000 0000 0007  
0684 0301 0000 0000 0000 0000 0000 0000  
0000 0000 0000 0000 0000 0000 0000 0000  
0000 0000 0000 0000 0000 0000 0000 0000  
0100 4000 121C 4007 FFFF FFFF FFFF FFFF  
FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF  
;
;-----------Range [0x40-0x7F]----------  
0000 0000 0000 0000 0000 0000 0000 0000  
0000 0000 0000 0000 0000 0000 0000 0000  
FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF  
FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF  
FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF  
FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF  
FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF  
FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF  
;
27  
 
 
NVM Information Guide—ICH8  
Note:  
This page intentionally left blank.  
28  
 

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